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ICs for Consumer Electronics
Quarter PIP Processor SDA 9189X (A123 / A132) 4PIP
Data Sheet 03.96
Edition 03.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 9189X Revision History: Previous Version: Page Page (in previous (in new Version) Version)
Current Version: 03.96
Subjects (major changes since last revision)
26.01.1994: Target Specification 15 30 32 36 38 30 35; 38 38 41 24 32; 36 33 34 35 36 38 41 43 46 47 49 51; 52 26.01.1994: not allowed display areas, display position 26.01.1994: character `m' instead of `%' 26.01.1994: bit D6 of register 0F inverted 26.01.1994: adjustment values VSIDEL 26.01.1994: DA converter 08.04.1994: character `&' instead of `!' 08.04.1994: text subaddress 06 and 0F 08.04.1994: output voltage ANACON 08.04.1994: supply voltage range 20.09.1994: examples for the adjustment of frame colors 20.09.1994: new I2C bits VSIISQ and VSPISQ 20.09.1994: notes at subaddress 00; bits D1 and D3 20.09.1994: note & warning at subaddress 02 20.09.1994: warning at subaddress 06 20.09.1994: warning at subaddress 07 20.09.1994: elimination of bit d6 of subaddress 0F 20.09.1994: output voltage 20.09.1994: remark for series resistance 20.09.1994: values supply current 20.09.1994: values DAC current 20.09.1994: new diagram 20.09.1994: new application circuit and layout proposal
SDA 9189X
Table of Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.5 2.5.1 2.5.2 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.8 2.8.1 2.8.2 2.8.3
Page
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decimation Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIP Field Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Picture Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Reading and Synchronization to Parent Channel . . . . . . . . . . . . . Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Standard of the PIP Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpolation of the Chrominance Signals . . . . . . . . . . . . . . . . . . . . . . . . . . Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Screen Background Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filling PIP Picture with Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wipe-In/Wipe-Out Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Formats and RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matrix Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Blanking Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pedestal for the Chrominance Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Video Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Control Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character and Character Background Luminance . . . . . . . . . . . . . . . . . . . . Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Receiver Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 19 19 19 20 21 21 21 22 22 22 23 23 24 24 25 25 25 26 26 26 26 27 27 27 27 27 27 28 29 30 30 30 30 31
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Table of Contents 3 3.1 3.2 3.3 4 4.1 4.2 4.2.1 4.2.2 4.3 4.3.1 5
Page 40 40 41 45 48 48 50 50 51 52 52
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Current of DA Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Board Layout Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Relation of Sync Pulses at Frame Mode . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I2C Bus Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
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General Description
The Picture Insertion Processor SDA 9189X generates a reduced size picture of an inset video channel for the purpose of combining it with another video signal (parent channel). The easy implementation of the IC into an existing system needs only a few additional external components. There is a great variety of application facilities in consumer and professional products (TV sets, VCRs, supervising monitors, multi-media, etc.).
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Quarter PIP Processor
SDA 9189X
Data Sheet 1.1 Features
* High system integration Filtering, field memory, RGB-matrix, DA-Conversion, clock generation, and control circuits integrated on one chip * 4 picture sizes 1/4th, 1/9th, 1/16th, or 1/36th of normal size P-DSO-32-2 * High resolution display 13.5 MHz/27 MHz display clock frequency 288 luminance and 72 chrominance pixels per inset line for picture size 1/4 6-bit amplitude resolution for each incoming signal component Frame mode display in single-PIP modes Horizontal and vertical filtering Special antialias filtering for the luminance signal * Single and multi PIP display Up to 9 pictures of 1/36th size (8 still and 1 moving) Up to 4 pictures of 1/16th size (3 still and 1 moving) Up to 2 pictures of 1/9th size (1 still and 1 moving) Up to 3 pictures of 1/9th size (2 still and 1 moving) as POP display in 16:9 TV sets (In multi-PIP modes only field mode display possible) * Multistandard applications Automatic recognition of 625 lines/525 lines standard (inset and parent channel) Scan conversion systems as flickerfree display systems (parent channel) * HDTV (parent channel) * 16:9 compatibility Operation in 4:3 and 16:9 TV sets 4:3 inset signals on 16:9 displays (picture size 1/4 and 1/9) 16:9 inset signals on 4:3 displays (picture size 1/9 and 1/16)
Type SDA 9189X
Semiconductor Group
Ordering Code Q67100-H5148
7
Package P-DSO-32-2
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SDA 9189X
* Digital inputs Y, + (B-Y), + (R-Y) Compatible with Triple ADC SDA 9187-2X * Analog outputs Y, + (B-Y), + (B-Y) or Y, - (B-Y), - (B-Y) or RGB 3 RGB-matrices: EBU, NTSC (Japan), NTSC (USA) * Digital to analog converter output e.g. for color decoder adjustment 6-bit resolution * Freely programmable position of inset picture Steps of 1 pixel and 1 line All PIP and POP positions are possible inside the standard display area * Programmable framing 4096 frame colors Variable frame width * Full screen background insertion 64 background colors or transparent display (parent picture seen) * Wipe-in/Wipe-out facility Start and end of insertion is the lower right PIP corner 4 periods programmable * Freeze picture * I2C Bus control * Up to three ICs in one application Three different I2C Bus addresses Up to 3 moving pictures using 3 ICs Up to 27 pictures of 1/36th size * On-screen display of channel index 64 characters programmable (alphanumeric and special symbols) 5 characters displayed in every PIP picture 4 different character luminance values (B-Y = R-Y = `0') 4 background luminance values (B-Y = R-Y = `0') or transparent mode (inset picture seen) * Numerical display PLL circuit for high stability clock generation * No necessity of PAL/SECAM delay lines when using suitable color decoders * P-DSO-32 package/350 mil (SMD) * 5 V supply voltage
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1.2
Pin Configuration (top view)
P-DSO-32-2
Figure 1
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1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1)
Pin Definitions and Functions Symbol VSI XIN XQ ADR Function1) Descriptions I/TTL I Q I3-L I/ana S S Q/ana Q/ana Q/ana Q/ana S S Q/var I/TTL I/TTL IQ/TTL I/TTL S I/TTL I/TTL I/TTL I/TTL I/TTL Inset vertical sync input PLL quartz oscillator input PLL quartz oscillator output I2C address DACs reference voltage DACs and PLL positive voltage supply Digital ground Analog output R or + (R-Y) or - (R-Y) Analog output G or Y Analog output B or + (B-Y) or - (B-Y) Analog output (e.g. color decoder adjustment) DACs and PLL ground Digital positive voltage supply Signals OUT1 - OUT3 valid Parent horizontal sync input Parent vertical sync input I2C data input/output I2C clock Digital ground Line locked clock inset picture Digital UV input data Digital UV input data Digital UV input data Digital UV input data
VREF VDDA VSS
OUT1 OUT2 OUT3 ANACON
VSSA VDD
SEL HSP VSP SDA SCL
VSS
LL3I UVIN0 UVIN1 UVIN2 UVIN3
S: supply, I: input, Q: output, TTL: digital (TTL), ana: analog, 3-L: 3 level signal, var: variable configuration of output stage (open source, open drain, TTL)
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1.3 Pin No. 25 26 27 28 29 30 31 32
1)
Pin Definitions and Functions (cont'd) Symbol YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 Function1) Descriptions I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL S I/TTL Digital Y input data Digital Y input data Digital Y input data Digital Y input data Digital Y input data Digital Y input data Digital positive voltage supply Inset horizontal sync input
VDD
HSI
S: supply, I: input, Q: output, TTL: digital (TTL), ana: analog, 3-L: 3 level signal, var: variable configuration of output stage (open source, open drain, TTL)
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1.4
Functional Block Diagram
Figure 2
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2 2.1
System Description Display Modes
8 single- and 10 multi-PIP display modes are available. Decimation, memory controlling, framing and on-screen display insertion depend on the selected display mode (PIPMOD). In the multi-PIP modes the complete inset picture can contain up to 9 partial pictures (see diagrams below). One of the partial pictures shows a moving picture, whereas the others show still pictures. The partial picture that has to be written is addressed via I2C Bus. The addresses (WRPOS) for the individual pictures are shown in the diagrams. The same addresses serve to choose the position of the moving picture. The multi-PIP modes allow tuner scanning. Four display modes are provided for applications with 16:9 inset signals or displays (see table 1). The single-PIP display modes 15 and 18 can be used to display 4:3 inset signals on 16:9 displays. To show 16:9 inset signals on 4:3 displays the single-PIP display modes 16 and 19 have been added. By means of multi-PIP display mode 17 a POP picture on a 16:9 display can be created. If a display mode is chosen that is not realized (modes 9, 12, and 20 to 31), the PIP insertion is switched off automatically (PIPON = `0'). Table 1 Display Mode (PIPMOD) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 (00000) (00001) (00010) (00011) (00100) (00101) (00110) (00111) (01000) (01001) (01010) (01011) (01100) (01101) Picture Size, Picture Configuration 1 x 1/4 1 x 1/9 1 x 1/16 1 x 1/36 4 x 1/16, 2 rows of 2 pictures 4 x 1/16, side by side 4 x 1/16, one upon another 9 x 1/36, 3 rows of 3 pictures 2 x 1/9, side by side Not realized (PIPON = `0') 8 x 1/36, 2 rows of 4 pictures 2 x 1/9, one upon another Not realized (PIPON = `0') 8 x 1/36, 2 columns of 4 pictures one upon another
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Table 1(cont'd) Display Mode (PIPMOD) 14 15 16 17 (01110) (01111) (10000) (10001) Picture Size, Picture Configuration 4 x 1/36, 2 rows of 2 pictures 1 x 1/9, 1 x 1/16, 3 x 1/9, 4:3 inset signal on 16:9 display horizontal decimation 4:1, vertical decimation 3:1 16:9 inset signal on 4:3 display horizontal decimation 3:1, vertical decimation 4:1 4:3 inset signals on 16:9 display horizontal decimation 4:1, vertical decimation 3:1 one upon another 4:3 inset signal on 16:9 display horizontal decimation 3:1, vertical decimation 2:1 16:9 inset signal on 4:3 display horizontal decimation 2:1, vertical decimation 3:1
18 19 20 31
(10010) (10011) (10100) : (11111)
1 x 1/4, 1 x 1/9,
Not realized (PIPON = `0')
The following diagrams show the various display modes. The figures on top of the rectangles give the width of the complete inset picture in pixels whereas the figures on the right specify its height by the number of lines. The values for the multi-PIP display modes are obtained by adding the widths and heights of the partial pictures. The sizes of the partial pictures correspond to the sizes of the inset pictures of the single-PIP modes (see below).
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288 192 0 126 (102) 0
84 (68)
Mode 0
Mode 1
144 96 0 Mode 2 63 (51) 0 Mode 3 42 (34)
288
0
1 126 (102)
2 Mode 4
3
576 0 Mode 5 Figure 3
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1
2
3
63 (51)
SDA 9189X
144 0 0 3 1 252 (204) 2 384 6 Mode 7
288 1 4 7 2 5 8 126 (102)
3 Mode 6 Mode 8 384 0 4 Mode 10 192 0 2 4 6 Mode 13 Figure 4
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0
1
64 (68)
192 2 6 3 84 (68) 0 168 (136) 1 7
1 5
1 Mode 11 3 5 7 168 (136) The display modes 9 and 12 are not realized. For a PIP display line standard of 525 lines the values in parenthesis are valid.
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192 0 1 84 (68) 2 Mode 14 3
144
192 63 (51)
0
84 (68) Mode 16
0
Mode 15
144
192
0 0 126 (102)
1
252 (204)
Mode 18
2
288
Mode 17
0
84 (68)
Mode 19
Figure 5
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2 ARD
1
-
3 ZDF
-
4 RTL
-
Figure 6 Multi-POP Feature at 16:9 Application with Display Mode 7 and OSD Main picture and one POP picture live, all other pictures still
5 - SFB
6 ORF
-
1 NDR
-
7 HR
-
8 NTV
-
4 RTL
-
2 ARD
3 ZDF
9 DFS
-
Figure 7 Multi-PIP Feature with Display Mode 7 Main picture and one PIP picture live, all other pictures still
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2.2 2.2.1
Input Signal Processing Data Transfer
The inset video signal is accepted as digital luminance and chrominance components with a 13.5 MHz clock for the luminance signal and a 3.375 MHz clock for the chrominance signals. Inset synchronization is done via pin HSI for horizontal and pin VSI for vertical synchronization. By analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. For applications with fixed line standard (625 lines or 525 lines) the automatic detection can be switched OFF. The phase of the vertical sync pulse is programmable (VSIDEL) (see chapter 4.3). This way a correct detection of the field number is possible, an important condition for frame mode display. 2.2.2 Decimation Window
A window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. The window has a width of 576 pixels for the luminance signal and a width of 144 pixels for the chrominance signals. In the vertical direction the window consists of 252 or 204 lines depending on the line standard (625 or 525 lines respectively). The horizontal position of this decimation window can be adapted to various applications with the help of a programmable delay of the luminance signal (HSIDEL) relative to the horizontal synchronization pulses. For HSIDEL = `0' the decimation window is opened 0 clock periods (13.5 MHz) after the horizontal synchronization pulse. For the 625 lines standard the 42th video line is the first decimated line, for the 525 lines standard decimation starts in the 38th video line.
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2.2.3
Decimation Filters
The input signal is decimated by subsampling with horizontal and vertical filtering. A special antialias filter improves the frequency response of the luminance channel. The following decimation filters are implemented: Horizontal Decimation 2:1 3:1 4:1 6:1 Vertical Decimation 2:1 3:1 4:1 6:1 Luminance Filter {11} {111} {1111} {111111} Luminance Filter {11} {111} {1111} {111111} Chrominance Filter {11} {121} {1111} {112211} Chrominance Filter {11} {121} {1111} {112211}
The realized chrominance filtering allows omitting the color decoder delay line for PAL and SECAM demodulation if the color decoder supplies the same output voltages independent of the kind of operation. In case of SECAM signals an amplification of the chrominance signals by a factor of 2 is necessary because there is a signal only in every second line. This chrominance amplification is programmable via I2C Bus (AMSEC).
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2.3
PIP Field Memory
The on-chip memory has a capacity of 329184 bits. It stores one decimated field of the inset picture. In the multi-PIP display modes the memory is able to store one decimated field of every partial picture (e.g. during tuner scanning). 2.3.1 Picture Sizes
The picture size depends on the horizontal and vertical decimation factors. Horizontal Decimation 2:1 3:1 4:1 6:1 Pixels/Line 288 192 144 96
Vertical Decimation 2:1 3:1 4:1 6:1 2.3.2
Lines/Field (625 lines standard) 126 84 63 42
Lines/Field (525 lines standard) 102 68 51 34
Memory Writing
To get equal clock frequencies for luminance and chrominance signals a multiplexer at the memory input generates a 3-bit data format for both chrominance components. In field mode display only every second inset field is written into the memory, in frame mode display the memory is written continuously. Data are written with the lower inset clock frequency depending on the horizontal decimation factor (6.75 MHz, 4.5 MHz, 3.375 MHz, or 2.25 MHz). Memory writing can be stopped by program (FREEZE), a freeze picture display results (one field). In single-PIP display modes frame mode display is possible having no scan conversion and the same number of lines in inset and parent channel (625 lines or 525 lines both). The result is a higher vertical and temporal resolution because of displaying every incoming field. The standards are analyzed internally and an activated frame mode display is switched to field mode display automatically when the described restrictions are no longer valid.
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2.3.3
Memory Reading and Synchronization to Parent Channel
The reading frequency is normally 13.5 MHz and 27 MHz for scan conversion systems. For progressive scan conversion systems and HDTV displays a line doubling mode is available (LINEDBL). Every line of the inset picture is read twice. Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals. These signals are fed to the IC at pin HSP for horizontal synchronization and at pin VSP for vertical synchronization. A numerical PLL circuit generates a clock signal that is locked to the horizontal synchronization pulses of the parent channel. The burst gate of the sandcastle signal can be used for horizontal synchronization. A field number detection is carried out for the inset channel as well as for the parent channel. Depending on the phase difference between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter. 2.4 2.4.1 Output Signal Processing Display Position
The display position of the inset picture is freely programmable (POSHOR, POSVER). The first possible picture position (without frame) is 55 clock periods (13.5 MHz or 27 MHz) after the horizontal and 7 lines after the vertical synchronization pulses. Starting at this position the picture can be moved over the whole display area. Even POP positions (Picture Outside Picture) can be used.
Note: Display without disturbances is only possible if the complete PIP picture is inside the visible area of the picture tube
POSHOR < 1 POSHOR < 864 - 2 x FRWIDH - PSH - 42 POSVER < 262 - 2 x FRWIDV - PSV - 8 POSVER < 312 - 2 x FRWIDV - PSV - 8 POS ... FRWID. PSH PSV
(60 Hz mode) or (50 Hz mode)
= Picture Position (see I2C Bus) = Frame Width (see I2C Bus) = Picture size horizontal (number of pixels) = Picture size vertical (number of line)
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2.4.2
Line Standard of the PIP Picture
The line standard used to display the complete PIP picture is programmable via I2C Bus (PIPLIN). The line standard of the parent channel or the inset channel can be used. In addition a fixed line standard of 625 or 525 lines can be chosen. Combinations of different line standards of the inset signal and the PIP display are handled in a special way: PIP display 625 lines, inset signal 525 lines - The inset picture is shifted down by 12, 8, 6, or 4 lines according to picture size. Due to this shift the centres of the inset pictures have the same position for both line standards. The remaining 12, 8, 6, or 4 lines at the top and the bottom of the inset picture are filled with the luminance value of the full screen background color (BCKY). The chrominance values are set to `0' for these parts of the inset picture. PIP display 525 lines, inset signal 625 lines - The inset picture is reduced to 102, 68, 51, or 34 lines. Depending on the number of lines the first and the last 12, 8, 6, or 4 lines are omitted. In this way the display shows the centre part of the original picture. Displaying multi-PIP pictures this procedure is applied individually to each of the partial pictures. 2.4.3 Interpolation of the Chrominance Signals
At the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sampling rate.
Semiconductor Group
23
03.96
SDA 9189X
2.4.4
Framing
In this part of the circuit a colored frame is added to the inset picture. 4096 frame colors are programmable, 4 bits for each component Y, (B-Y), (R-Y). The horizontal and vertical widths of the frame are independently programmable. In the multi-PIP modes the various partial pictures are separated by inner frame elements. These parts of the frame have a fixed horizontal width of 4 pixels and a fixed vertical width of 2 lines. For INFR = `0' the inner frame elements are not inserted. The outer frame elements border on the inset picture without limiting its size whereas the inner frame elements reduce the areas of the partial pictures. Examples for the Adjustment of Frame Colors Frame Color FRY D3 ... D0 of Subaddress 09 0100 0100 1100 0100 1100 1100 0100 FRU D3 ... D0 of Subaddress 0A 0110 1000 0000 1000 1000 0010 0110 FRV D7 ... D4 of Subaddress 0A 1010 1010 0000 0111 0100 1010 0100
Blue Green White Red Yellow Cyan Magenta 2.4.5
Full Screen Background Insertion
Instead of showing the parent picture it is possible to fill the background (full screen picture without inset picture and its frame, BCKON = `1') with a programmable color. For BCKFR = `1' the background color is identical with the frame color, otherwise it is defined by 6 bits programmable via I2C Bus: two bits for each component. The bits for the chrominance signals are used directly as MSBs of the output words B-Y and R-Y. The remaining LSBs are set to `0'. Therefore 16 different colors are possible. The two bits for the Y-signal choose a luminance value according to the following table (100 IRE corresponds to the full scale range of DAC input = integer value 63): Background Luminance 00 01 10 11
Semiconductor Group
IRE 20 30 40 50
24
Integer Value 12 19 25 31
03.96
SDA 9189X
2.4.6
Filling PIP Picture with Color
The whole inset picture can be filled with the frame color (FRCOL = `1') or the luminance value for the full screen background insertion without colors (BCKCOL = `1', FRCOL = `0'). The frame elements remain visible. Filling the PIP picture with background is especially useful before starting a tuner scanning cycle. 2.4.7 Wipe-In/Wipe-Out Facility
With the wipe-in/wipe-out function it is possible to make appear or disappear the complete inset picture starting or ending at the lower right corner of the inset picture position. Thereby the size of the picture is continuously increased and decreased respectively. During this procedure the frame is shown with its chosen widths. 4 different periods are programmable via I2C Bus. 2.4.8 Output Formats and RGB Conversion
Different output formats are available: luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB signals. For the RGB conversion 3 matrices are provided: Standard B-Y EBU NTSC (Japan) NTSC (USA) 1 1 1 Amplitudes R-Y 0.558 0.783 1.013 G-Y 0.345 0.31 0.305 B-Y 0 0 0 Angles R-Y 90 95 104 G-Y 237 240 252
Matrix selection is done via I2C Bus. The matrices are designed for the following voltages at the inputs of the ADC converter (the values correspond to 100 % white and 75 % color saturation): Component Y B-Y R-Y Input Voltage (without Sync) in % of Full Scale Input Range of ADC 75 100 100
Semiconductor Group
25
03.96
SDA 9189X
2.4.9
Matrix Equations EBU
R G= B
1 0 1 - 0.25 0.78125 1 - 0.1875 - 0.40625 1
B-Y R-Y Y
NTSC (Japan)
R G= B
1 0 1 - 0.0625 1.09375 1 - 0.15625 - 0.375 1
B-Y R-Y Y
NTSC (USA)
R G B
=
1 0 1 B-Y - 0.25 1.375 1 R - Y - 0.09375 - 0.40625 1 Y
2.4.10 Select Signal For controlling an external fast switch (for example an RGB processor) a select signal SEL is supplied. The delay of this signal relative to the luminance and chrominance components is programmable for adaption to different external output signal
Semiconductor Group 26 03.96
SDA 9189X
processings. Three different characteristics of the output stage of this signal are available. An open source, an open drain, or a TTL output can be selected via I2C Bus (SELMOD). 2.4.11 Blanking Signals In case of full screen background insertion the circuit has to generate output signals with correctly positioned line blanking intervals relative to the horizontal synchronization pulses of the parent channel. This can be achieved by a programmable delay (BLKDEL). A field-blanking interval with a length of 16 lines is also provided. It is triggered by the vertical synchronization pulse of the parent channel (VSP). The generation of this field-blanking signal can be activated via I2C Bus (VERBLK = `1'). 2.4.12 Pedestal for the Chrominance Signals Both components of the chrominance signal are equipped with a programmable pedestal (white balance, PEDESTU, PEDESTV). The pedestal values are fed to the digital to analog converters during the line blanking intervals. For each component a 4-bit value in 2's complement code is defined via I2C Bus. Building up the 6-bit input words of the digital to analog converters these 4 bits are used as LSBs. The missing two MSBs are complemented by sign extension. In this way pedestal values from - 8 to + 7 LSBs of the digital to analog converters can be achieved. 2.5 2.5.1 Digital-to-Analog Conversion Analog Video Outputs
The IC includes three 6-bit digital to analog converters for the video outputs. Each converter supplies a current through an external resistor that is placed between VSSA and OUT1, OUT2, OUT3 respectively. The current is controlled by a digital control circuit. 2.5.2 Analog Control Signal
The additional 6-bit digital to analog converter that provides an analog control signal (e.g. for color decoder adjustment) is fed directly by a 6-bit signal programmable via I2C Bus. No external resistor is needed at output ANACON. 2.6 2.6.1 On-Screen Display Display Format
The on-screen display allows to insert a block of 5 characters into each of the PIP pictures. The characters are placed in a box (background) with a width of 64 pixels and a height of 12 lines. This box is situated in the upper left corner of the PIP pictures. The
Semiconductor Group
27
03.96
SDA 9189X
background box can be made transparent (CHARBCK = `0'), i.e. behind the characters the inset picture becomes visible. 64 different characters are stored in a character ROM (see table 2). Each character is defined by a pixel matrix consisting of 10 lines and 12 pixels per line. 2.6.2 Character Programming
The 5 characters per block are programmable via I2C Bus using a 7-bit code which is identical with the ASCII code except for some of the special characters. The codes are placed in a character RAM consisting of 45 cells. The size of the RAM is determined by the number of characters per block (5) and the maximum number of PIP pictures (9 in multi-PIP display modes). The character codes can be transmitted in two ways: each of the 45 RAM locations can be reached separately by its 7-bit address or the RAM can be written consecutively starting at an arbitrarily chosen position. In this case the RAM address is increased automatically. The 7-bit address consists of two parts: the 4 MSBs are used to choose one of the partial pictures and the 3 LSBs to select one of the 5 characters per block.
Semiconductor Group
28
03.96
SDA 9189X
2.6.3
Character and Character Background Luminance
The chrominance components of the characters and their background box always have the value `0'. The luminance values are programmable via I2C Bus according to the following tables (100 IRE corresponds to the full scale range of DAC input = integer value 63): Table 2 IRE Character Luminance 00 01 10 11 Character Background Luminance 00 01 10 11 10 20 30 40 6 12 19 25 60 70 80 90 38 44 50 56 Integer Value
Semiconductor Group
29
03.96
SDA 9189X
2.6.4
Character Set
0000001=01
0000010=02
0000011=03
0000100=04
0000101=05
0000110=06
0000111=07
0001000=08
0001001=09
0001010=0A
0001011=0B
0100000=20
0100001=21
0100011=23
0100100=24
0100101=25
0101010=2A
0101011=2B
0101101=2D
0101111=2F
0110000=30
0110001=31
0110010=32
0110011=33
0110100=34
0110101=35
0110110=36
0110111=37
0111000=38
0111001=39
0111100=3C
0111101=3D
0111110=3E
0111111=3F
1000001=41
1000010=42
1000011=43
1000100=44
1000101=45
1000110=46
1000111=47
1001000=48
1001001=49
1001010=4A
1001011=4B
1001100=4C
1001101=4D
1001110=4E
1001111=4F
1010000=50
1010001=51
1010010=52
1010011=53
1010100=54
1010101=55
1010110=56
1010111=57
1011000=58
1011001=59
1011010=5A
1011011=5B
1011101=5D
1011110=5E
1011111=5F
Figure 8 This figure shows the pixel matrices of the characters stored in the character ROM.
Semiconductor Group
30
03.96
SDA 9189X
2.7
Numerical PLL
A numerical PLL circuit supplies a clock of about 27 MHz with high stability. The nominal quartz frequency is 20.48 MHz. The generated clock is locked to the parent horizontal synchronization pulses. Its frequency varies with the frequency of this signal. Four different characteristics of the PLL behavior can be chosen to handle synchronization signals from various sources (PLLTC). If the PLL is switched OFF an external 13.5 or 27 MHz parent line locked clock can be fed to the IC. Using up to three SDA 9189X ICs in the same application only one quartz is necessary.
Note: Before setting bit D3 of subaddress 00 (READ27) noise reduction of the VSP pulse must be switched OFF (D5 of subaddress 08 = `1').
2.8 2.8.1 I2C Bus I2C Bus Addresses
Three different I2C Bus addresses are programmable via pin ADR. Pin ADR Low level (VSS or VSSA) Mid level (open) High level (VDD or VDDA) 2.8.2 S S: A: P: I2C Bus Receiver Format 0 A Subaddress A Data Byte A *** A P Address (BIN) 1101011 1101110 1101111 Address (HEX) D6 DC DE
Address
Start condition Acknowledge Stop condition
Only write operation is possible. An automatical address increment function is implemented.
Semiconductor Group
31
03.96
SDA 9189X
2.8.3
I2C Bus Commands
Overview
Sub add. (Hex.) D7 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 0 0 Data Byte D6 0 SELDEL3 D5 FREEZE SELDEL2 D4 PLLOFF SELDEL1 D3 READ27 SELDEL0 D2 LINEDBL VERBLK D1 FRAME D0 PIPON
POSHOR9 POSHOR8
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 POSVER7 POSVER6 0 WRPOS3 0 AMSEC 0 CON3 FRV5 INFR 0 0 PIPLIN1 WRPOS2 0 0 0 CON2 FRV4 SELMOD1 0 PLLTC1 POSVER5 PIPLIN0 WRPOS1 BCKCOL VSIISQ VSPISQ CON1 FRV3 SELMOD0 0 PLLTC0 POSVER4 PIPMOD4 WRPOS0 HSIDEL4 VSIDEL4 VSPDEL4 CON0 FRV2 FRWIDV1 0 0 POSVER3 PIPMOD3 PMOD1 HSIDEL3 VSIDEL3 VSPDEL3 FRY5 FRU5 FRWIDV0 MAT1 0 POSVER2 PIPMOD2 PMOD0 HSIDEL2 VSIDEL2 VSPDEL2 FRY4 FRU4 FRWIDH2 MAT0 0 POSVER1 PIPMOD1 IMOD1 HSIDEL1 VSIDEL1 VSPDEL1 FRY3 FRU3 FRWIDH1 CHRPIP 0 POSVER0 PIPMOD0 IMOD0 HSIDEL0 VSIDEL0 VSPDEL0 FRY2 FRU2 FRWIDH0 OUTFOR 0
PEDESTV3 PEDESTV2 PEDESTV1 PEDESTV0 PEDESTU3 PEDESTU2 PEDESTU1 PEDESTU0 DACONST 0 BCKFR WIPEON 0 0 0 BCKY1 WIPESP1 CHARY1 ANCON5 BCKY0 WIPESP0 CHARY0 ANCON4 BCKU5 BLKDEL3 CHBCKY1 ANCON3 BCKU4 BLKDEL2 CHBCKY0 ANCON2 BCKV5 BLKDEL1 ANCON1 BCKV4 BLKDEL0 ANCON0 BCKON FRCOL
CHARBCK CHARRES OSDON
CHARLOC6 CHARLOC5 CHARLOC4 CHARLOC3 CHARLOC2 CHARLOC1 CHARLOC0 CHAR6 CHAR5 CHAR4 CHAR3 CHAR2 CHAR1 CHAR0
After switching on the IC the data bytes of all registers are set to `0', the bit PLLOFF is set to `1'.
Semiconductor Group
32
03.96
SDA 9189X
Detailed Description Bit Name Function
Subaddress 00 D5 D4 D3 FREEZE PLLOFF READ27 0: moving picture 1: freeze picture 0: internal PLL ON 1: internal PLL OFF (external clock generation) 0: PIP display with single-read frequency (13.5 MHz) 1: PIP display with double read frequency (27 MHz) (see note page 31) 0: each line of the PIP memory is read once (normal operation) 1: each line of the PIP memory is read twice (line doubling for progressive scan conversion systems in parent channel) 0: field mode display 1: frame mode display (if possible). Correct adjustment of bits VSIDEL, VSPDEL required (see chapter 4.3). 0: PIP insertion OFF 1: PIP insertion ON
D2
LINEDBL
D1
FRAME
D0
PIPON
Subaddress 01 D6 ... D3 SELDEL D2 VERBLK Delay of output signal at pin SEL (- 8 ... + 7 periods of read frequency clock, programmable in 2's complement code) 0: clamping level at DAC outputs only during line blanking intervals 1: clamping level at DAC outputs during line blanking intervals and field-blanking intervals (16 complete lines following the vertical synchronization pulse of the parent channel) 2 MSBs of POSHOR (see Subaddress 02 on page 34)
D1 ... D0 POSHOR
Semiconductor Group
33
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 02 D7 ... D0 POSHOR Horizontal position of PIP picture (in steps of 1 pixel) Note: the 2 MSBs of POSHOR are located at subaddress 01, bits D0 and D1. Warning: Positions outside the active area of the parent picture are possible. Allowed area see at chapter 2.4.1. To avoid horizontal jumping of the picture by changing POSHOR from `00 1111 1111' to `01 0000 0000' its necessary to transfer the bits of both subaddresses during the same field period. Subaddress 03 D7 ... D0 POSVER Vertical position of PIP picture (in steps of 1 line) Warning: Positions outside the active area of the parent picture are possible. Allowed area see at chapter 2.4.1
Subaddress 04 D6 ... D5 PIPLIN 00: 01: 10: 11: PIP display line standard according to parent signal PIP display line standard according to inset signal fixed PIP display line standard: 625 lines fixed PIP display line standard: 525 lines
D4 ... D0 PIPMOD
Display mode (8 single- and 10 multi-PIP display modes are available, see diagrams above)
Semiconductor Group
34
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 05 D7 ... D4 WRPOS Multi-PIP diplay modes: selection of partial picture for writing (position number depends on the chosen display mode, see diagrams). At single-PIP display modes WRPOS must be set to `0000'. 00: 01: 10: 11: 00: 01: 10: 11: automatic detection of line standard (parent signal) fixed adjustment 625 lines fixed adjustment 525 lines freeze last line standard automatic detection of line standard (inset signal) fixed adjustment 625 lines fixed adjustment 525 lines freeze last line standard
D3 ... D2 PMOD
D1 ... D0 IMOD
Subaddress 06 D5 BCKCOL 0: inset pictures visible (normal mode) 1: PIP picture filled with luminance value of the background color BCKY (see Subaddress 10 on page 38). The chrominance components are set to `0'. Delay of the horizontal synchronization pulse of the inset signal (in steps of 4 periods of 13.5 MHz clock) for the purpose of shifting the decimated part of a line. Warning: adjustment of HSIDEL will influence the adjustment of VSIDEL (subaddr. 07) (see chapter 4.3).
D4 ... D0 HSIDEL
Semiconductor Group
35
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 07 D7 AMSEC 0: unity amplification of decimation filters (normal mode) 1: amplification by a factor of 2 (SECAM signals without delay line in the chroma decoder) Noise reduction of the VSI pulse (should be set to `0' under normal conditions) Delay of vertical synchronization pulse of the inset signal (in steps of 32 periods of 13.5 MHz clock) Warning: Correct adjustment value is influenced by the adjustment of HSIDEL (subaddr. 06; see chapter 4.3).
D5
VSIISQ
D4 ... D0 VSIDEL
Subaddress 08 D5 VSPISQ Noise reduction of the VSP pulse (should be set to `0' under normal conditions) In case changing from standard mode to line or frame conversion modes, `1' should be set during the changement of line frequency. Delay of vertical synchronization pulse of the parent signal (in steps of 32 periods of the read clock with a frequency of 13.5 or 27 MHz)
D4 ... D0 VSPDEL
Subaddress 09 D7 ... D4 CON D3 ... D0 FRY Subaddress 0A D7 ... D4 FRV D3 ... D0 FRU Chrominance component (R-Y) of frame color (4 MSBs of 6 bits) Chrominance component (B-Y) of frame color (4 MSBs of 6 bits) Contrast adjustment of PIP picture (16 steps) Luminance component of frame color (4 MSBs of 6 bits)
Semiconductor Group
36
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 0B D7 INFR 0: inner frame elements OFF 1: inner frame elements ON 00: TTL output 01: open source output 10: open drain output Vertical width of PIP frame (0 ... 3 lines) Horizontal width of PIP frame (0 ... 7 pixels)
D6 ... D5 SELMOD
D4 ... D3 FRWIDV D2 ... D0 FRWIDH Subaddress 0C D3 D2 D1 D0 MAT1 MAT0 CHRPIP OUTFOR
0: NTSC RGB matrix (USA) 1: NTSC RBG matrix (Japan) 0: EBU RGB matrix 1: NTSC RGB matrix 0: non-inverted chrominance output signals + (B-Y), + (R-Y) 1: inverted chrominance output signals - (B-Y), - (R-Y) 0: format of output signals: Y, (B-Y), (R-Y) 1: format of output signals: R G B
Subaddress 0D D6 ... D5 PLLTC 00: PLL loop filter: medium damping, low res. frequency 01: PLL loop filter: low damping, high res. frequency 10: PLL loop filter: high damping, low res. frequency 11: PLL loop filter: medium damping, high res. frequency Note: After power on PLLTC must remain at 00 until system is locked.
Semiconductor Group
37
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 0E D7 ... D4 PEDESTV 4-bit pedestal value for chrominance component (R-Y) fed to corresponding DAC during line-blanking interval (2's complement code, - 8 to + 7 LSBs of DAC) 4-bit pedestal value for chrominance component (B-Y) fed to corresponding DAC during line blanking interval (2's complement code, - 8 to + 7 LSBs of DAC)
D3 ... D0 PEDESTU
Subaddress 0F D7 DACONST Changing from `0' to `1' starts automatic adjustment of OUT1 ... 3 output current. Digital input value for DAC at output pin ANACON (2's complement code, all bits `0' = medium output voltage)
D5 ... D0 ANCON
Subaddress 10 D7 BCKFR 0: color of full screen background insertion according to the settings of BCKY, BCKU, and BCKV 1: color of full screen background insertion identical with the frame color 00: 01: 10: 11: luminance value of full screen background: 20 IRE luminance value of full screen background: 30 IRE luminance value of full screen background: 40 IRE luminance value of full screen background: 50 IRE
D6 ... D5 BCKY
D4 ... D3 BCKU D2 ... D1 BCKV D0 BCKON
2 MSBs of chrominance component (B-Y) of full screen background (remaining bits = `0') 2 MSBs of chrominance component (R-Y) of full screen background (remaining bits = `0') 0: full screen background insertion OFF 1: full screen background insertion ON
Semiconductor Group
38
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 11 D7 WIPEON 0: wipe-in/-out function OFF 1: wipe-in/-out function ON Period for opening and closing the PIP window 4 values from 1/3 to 4/3 of a second can be selected (WIPESP = 00 corresponds to the shortest time period) Delay to adjust line blanking interval (parent channel, full background insertion) in steps of 8 periods of 13.5 MHz/27 MHz clock 0: inset pictures visible (normal mode) 1: PIP picture filled with frame color
D6 ... D5 WIPESP
D4 ... D1 BLKDEL
D0
FRCOL
Subaddress 12 D6 ... D5 CHARY 00: 01: 10: 11: luminance value of character 60 IRE luminance value of character 70 IRE luminance value of character 80 IRE luminance value of character 90 IRE luminance value of character background: 10 IRE luminance value of character background: 20 IRE luminance value of character background: 30 IRE luminance value of character background: 40 IRE
D4 ... D3 CHARBCKY 00: 01: 10: 11: D2 D1 D0 CHARBCK CHARRES OSDON
0: character background insertion OFF 1: character background insertion ON 0: characters unchanged 1: all characters set to special character `blank' 0: on screen display of characters OFF 1: on screen display of characters ON
Semiconductor Group
39
03.96
SDA 9189X
Detailed Description (cont'd) Bit Name Function
Subaddress 13 D6 ... D0 CHARLOC 7-bit address of character RAM: 4 MSBs address partial pictures (0 to 8 max.), 3 LSBs address character position in block (0 to 4, from left to right)
Subaddress 14 D6 ... D0 CHAR Character code to select 1 of 64 available characters
Semiconductor Group
40
03.96
SDA 9189X
3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol min. Limit Values max. 70 125 125 260 10 -1 -1 7 7 C C C C s V V Under all conditions at pins XQ, OUT1 ... 3; pins XQ, OUT1 ... 3 0 - 55 Unit Remark
Parameter Ambient temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages
TA Tstg Tj TSOLD
Soldering time tSOLD
VI VQ
VDD + 0.5 V VDD
-1 - 0.25 7 0.25 900 -1 1 V V mW kV
Supply voltage VDD D differentials Total power dissipation ESD protection
Ptot
ESD
MIL STD 883C method 3015.6 100 pF, 1500 supply pins connected to ground Except analog outputs, XQ
Latch-up protection
- 100
100
mA
Note: All voltages listed are referenced to ground (0 V, VSS) except where noted. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
Semiconductor Group 41 03.96
SDA 9189X
3.2
Operational Range Symbol Limit Values min. typ. 5 25 max. 5.5 70 V C 4.75 0 Unit Remark
Parameter Supply voltages Ambient temperature All TTL Inputs
VDDxx TA
Low-level input voltage VIL High-level input voltage VIH
-1 2.0
0.8 6
V V
Inset Horizontal Sync TTL Input: HSI1) Horizontal frequency Signal rise time Signal high time Signal low time Signal setup time 100 900 15 14.53 16.72 kHz 15 ns ns ns ns LH transition of LL3I
Inset Vertical Sync TTL Input: VSI1) Signal high time Signal low time 200 200 ns ns
Line Locked Clock Inset Picture TTL Input: LL3I1) Signal period time Signal rise time Signal fall time Signal high time Signal low time
1)
68
80 5 4
ns ns ns ns ns
28 30
All values are referred to the corresponding min (VIH) and max (VIL).
Semiconductor Group
42
03.96
SDA 9189X
3.2
Operational Range(cont'd) Symbol Limit Values min. typ. max. Unit Remark
Parameter
Digital Data TTL Inputs: YIN, UVIN1) Signal setup time Signal hold time 15 5 ns ns LH transition of LL3I LH transition of LL3I
Parent Horizontal Sync TTL Inputs: HSP1) Sync frequency in single-frequency display mode Sync frequency in double frequency display mode Signal rise time Signal high time Signal low time 100 900 14.53 15 29.06 30 16.72 kHz 17.19 kHz 33.44 kHz 34.38 kHz 100 ns ns ns Quartz frequency 20.48 MHz Quartz frequency 21.09 MHz Quartz frequency 20.48 MHz Quartz frequency 21.09 MHz Noisefree transition
Parent Vertical Sync TTL Input VSP1) Signal high time Signal low time Quartz/Ceramic Resonator Recommended frequency Series resistance 20.25 20.48 21.3 10 20 30 40
1)
200 200
ns ns
MHz 21.09 MHz for MUSE
C1, C2 33 pF C1, C2 22 pF C1, C2 15 pF C1, C2 10 pF
All values are referred to the corresponding min (VIH) and max (VIL).
Semiconductor Group
43
03.96
SDA 9189X
3.2
Operational Range(cont'd) Symbol Limit Values min. typ. max. Unit Remark
Parameter
Optional TTL Clock Input: XIN1) Clock input cycle time Clock input rise time Clock input fall time Clock input low time Clock input high time Fast I2C Bus1) 2) SCL clock frequency Inactive time before start of transmission Setup time start condition Hold time start condition SCL low time 10 10 35 40 5 5 ns ns ns ns ns External line locked 27 MHz clock (I2C: internal PLL OFF)
fSCL tBUF tSU; STA tHD; STA
400 1.3 0.6 0.6 1.3 0.6 100 0 20 + $ 0.6 400 0.9 300
kHz s s s s s ns s ns s pF $ = 0.1Cb/pF
tLOW SCL high time tHIGH Setup time DATA tSU; DAT Hold time DATA tHD; DAT SDA/SCL rise/fall times tR, tF Setup time stop tSU; STO
condition Capacitive load/bus line Cb
1) 2)
All values are referred to the corresponding min (VIH) and max (VIL). This specification of the bus does not have to be identical with the I/O stages specification because of optional series resistors between bus lines and I/O pins.
Semiconductor Group
44
03.96
SDA 9189X
3.2
Operational Range(cont'd) Symbol Limit Values min. typ. max. Unit Remark
Parameter
I2C Bus Inputs/Output: SDA, SCL High-level input voltage VIH Low-level input voltage VIL Spike duration at inputs Low-level output current 3 - 0.5 0 0
VDD + V
0.5 1.5 50 6 V ns mA
Also for SDA/SCL input stages
IOL
I2C Bus Three Level Input ADR High-level input voltage VIH Low-level input voltage VIL Medium-level voltage 3.5 -1 6 0.8 V V open input, see chapter 3.3
VIM
Digital to Analog Converters (6 bit) OUT1, OUT2, OUT3 Full range output voltage Reference resistance
VOFR RREF1
4.2
1 5.1
2 6.3
V k
Peak to peak No contrast adjustment via I2C Bus; bits CON = `0000' Contrast adjustment via I2C Bus
Reference resistance
RREF2
6.0
6.8
7.5
k
Note: In the operational range the functions given in the circuit description are fulfilled.
Semiconductor Group
45
03.96
SDA 9189X
3.3
Characteristics Symbol Limit Values min. max. 160 mA Unit Remark
(assuming operational range) Parameter Average total supply current
IDDtot
IDDtot = IDD + IDDA
Note: The maxima do not necessarily coincide.
Average digital supply current Average analog supply current
IDD IDDA
140 35
mA mA
All digital Inputs (TTL, I2C) Input capacitance Input leakage current
CI
- 10
7 10
pF A
Not tested Including leakage current of SDA output stage, not pin XIN; V=0...5V Pin XIN; V = 0 ... 5 V
Input leakage current Output SEL High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage Leakage current Output capacitance I2C Bus Inputs: SDA/SCL Schmitt trigger hysteresis
Semiconductor Group
- 0.4
0.4
mA
VOH VOH VOL VOL
2.4 V 1.5 V 0 0 - 10
VDD VDD
0.4 1
1 1 V V A
IOH = - 200 A
SELMOD = 00 or 01
IOH = - 4.5 mA
SELMOD = 00 or 01
IOL = 1.6 mA
SELMOD = 00 or 10
IOL = 5 mA
SELMOD = 00 or 10
VO = 0 V ... VDD
Not tested
7
pF
Vhys
0.2
46
V
Not tested
03.96
SDA 9189X
3.3
Characteristics (cont'd) Symbol Limit Values min. max. Unit Remark
(assuming operational range) Parameter
I2C Bus Input/Output: SDA1) Low-level output voltage Low-level output voltage Output fall time from min (VIH) to max (VIL)
VOL VOL tOF
0.4 0.6 20 + 250 0.1Cb/pF
V V ns
IOL = 3 mA IOL = max 10 pF Cb 400 pF
I2C Bus Three-Level Input ADR Differential input resistor
RIN
6
16
k
Digital-to-Analog Converters (6 bit): Current Source Outputs OUT1, OUT2, OUT32) D.C. diff. linearity error Full range output current DLE - 0.5 - 1.25 0.5 - 1.69 LSB RREF = 5.1 k mA
IO
VDDA = nom, TA = nom, RREF = 5.1 k, RL = 680 ,
after adjustment
Output voltage VO (VO ~ 1.6 x VDDA x RL/RREF) Tracking
0.85 -3
1.15 3
V %
Contrast increase
30
%
TA = nom, RL = 680 RREF = 5.1 k VDDA = nom, TA = nom, RREF = 5.1 k, RL = 680 VDDA = nom, TA = nom, RL = 680 , RREF = 6.8 k, contrast
bits change from `0000' to `1111'
1)
2) I2C:
Referenced to SCL; open drain output. contrast bits set to zero unless otherwise noted.
Semiconductor Group
47
03.96
SDA 9189X
3.3
Characteristics (cont'd) Symbol Limit Values min. max. Unit Remark
(assuming operational range) Parameter
Static Digital-to-Analog Converter (6 bit): Analog Voltage Output ANACON D.C. diff. linearity error Low-level output voltage High-level output voltage High-level output voltage DLE -1 0.3 1 0.7 LSB V 1 1
VOL VOH VOH
VDDA
- 0.5 V
VDDA VDDA
RL 10 k RL 100 k RL 10 k
VDDA
- 0.9 V
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
48
03.96
SDA 9189X
4 4.1
Diagrams Output Current of DA Converters
Nominal values: VDDA = 5 V; RREF = 5.1 k; T = 25 C Measurements after adjustment via bit d7 of I2C Bus address 0F for each step
Note: The output currents are controlled in digital way, so inaccuracy of 1 LSB (ca. 2 %) is always possible.
Output Current = f (VDDA) Output Current = f (TA)
Semiconductor Group
49
03.96
SDA 9189X
Output Current = f (RREF)
Output Current = f (CON 0 ... 3)
Semiconductor Group
50
03.96
SDA 9189X
4.2 4.2.1
Application Information Application Circuit
Figure 9
Semiconductor Group 51 03.96
SDA 9189X
4.2.2
Application Board Layout Proposal
Figure 10 (top view)
Figure 11 (bottom view)
Semiconductor Group 52 03.96
SDA 9189X
4.3 4.3.1
Waveforms Phase Relation of Sync Pulses at Frame Mode
Figure 12 Signal Flow of the Horizontal Synchronization (insert part)
Figure 13 Allowed Phase Relation of the Horizontal/Vertical Sync Pulses (insert channel) if VSIDEL (0:4) = `0000'
Semiconductor Group 53 03.96
SDA 9189X
Figure 14 Allowed Phase Relation of the Horizontal/Vertical Sync Pulses (parent channel) if VSPDEL (0:4) = `0000'
Semiconductor Group
54
03.96
SDA 9189X
5
Package Outlines P-DSO-32-2 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book `Package Information' SMD = Surface Mounted Device Semiconductor Group 55
Dimensions in mm
03.96
GPS05697

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